1. Field of the Invention This invention relates generally to a data processing system in which a program being executed in a guest virtual computer accesses plural space operands concurrently, and more particularly to a method of accessing multiple virtual address spaces by means for storing translation pairs each consisting of a space identifier (hereinafter called "space iD") and a translation pair of an origin address.
2. Description of the Related Art
Conventionally, in data processing systems employing virtual addressing in multiple virtual storage spaces, the range which can be designated by an instruction with a logical address obtained by using, for example, a general register is called "a virtual address space". From this virtual address space and a logical address, a real storage address is given by a computer system. The operation to obtain a real address from a virtual address space and a logical address is called "address translation". This address translation is performed, for every virtual address space, by using address translation tables (i.e., a segment table and a page table) predetermined by the computer system.
The address translation tables exist on a main storage, and its origin address (STO: Segment Table Origin address) is given for every virtual address space. Address translation from a logical address into a real address is performed by referring to the address translation tables by using the origin address STO.
Further, for determining an address space from multiple virtual address spaces, a space iD is designated by a base access register corresponding to a base register to be used in computing an operand logical address of an instruction, and the STO corresponding to this space iD can be obtained by means for referring to the tables provided in the computer system. This prior art is exemplified by Japanese Patent Publication No. 41379/1985 and its corresponding U.S. Pat. No. 4,521,846.
For more advanced prior art, a method was proposed in which a translation pair of a space iD and STO are prestored in hardware when a base access register is used for memory accessing.
In this prior art, when an ordinary memory access instruction, e.g., an L (load) instructions is inputted in an instruction register, a base register is selected from the general registers, for calculating a logical address of an operand according to four bits of a base register number field, and at the same time, a base access register paired with the base register is selected, thereby determining STO. Specifically, using a space iD in the base access register, reference is made to a memory in which translation pairs of space iDs and STOs are stored, and an STO corresponding to the space iD of an operand is readout, whereupon the logical address of the operand is translated into a real address based on the STO to access a buffer storage or a main storage. If a desired translation pair consisting of the space iD and the STO is not stored in the translation pair memory, it is possible to obtain the STO by operating an access register translation table in the main storage by hardware (this is called "access register translation"). After this access register translation, a buffer storage or a main storage are accessed in the same manner as discussed above.
In such processing, when a translation table defining the translation of the space iD and the STO is altered, there is a possibility that a translating pair consisting of the space iD and the STO before the alteration could be stored in the translation pair memory. For this reason, there is prepared an instruction by which the translation pair stored in the translation pair memory is invalidated.
With the above-mentioned prior art, when a reference is made to a translation pair memory of space iDs and STOs by a given space iD during operation of a guest virtual computer in a virtual computer system, there is a possibility to read a translation pair, though with the same space iD, which was stored by a host or other guest virtual computer other than the guest virtual computer. If real address translation is performed with this STO, a wrong access to a buffer storage or a main storage would be carried out.
Consequently, at the start or termination of operation of the guest virtual computer, the host computer must issue an instruction for invalidating the whole translation pair memory or must exclusively allocate the space iD to the host computer and the individual guest virtual computers.
However, in the former method, the translation processes of space iDs to STOs are increased due to the invalidation of the translation pair memory, while in the latter method, the exclusive allocations of the space iD to be performed by the host computer would degrade the performance of the system. Further, when the instruction for invalidating the translation pair memory is issued during operation of the guest virtual computer, even the translation pairs stored by the host and other guest virtual computers would be invalidated. As a result, also in the host and other guest virtual computer, the translating process of the space iD to the STO would increase, thus degrading the performance.